The first question design teams need to consider is what functional blocks and functions will be included in a design and how those functions will be partitioned into different chiplets. Additionally, ...

Intel’s expansion; Cadence AI super agent for PCB, advanced packaging; photonics fab wars; earlier Yongin fab; German funding; new CHIPS Act award; HBM standard; Quadric funding; AMS acquisition; ...

A realistic virtual model uncovers the impact of rounded corners on sensitivity to overlay-induced resistance.

If one AI agent can solve a problem in a certain amount of time, can multiple agents solve it faster? The answer is yes, but only if the agents have well-defined roles and targets. This is where ...

Newer nonvolatile memory (NVM) technologies are poised to take over from flash in embedded applications on newer process ...

The three leading-edge foundries — Intel, Samsung, and TSMC — have started filling in some key pieces in their roadmaps, adding aggressive delivery dates for future generations of chip technology and ...

An Industry 4.0 technology roadmap for semiconductor device makers that covers carbon emissions, water, and hazardous waste.

Hybrid bonding already works in production, but finer-pitch die-to-wafer integration must preserve fab-level surface and ...

AI opens the door to exploring a much larger solution space, similar to what high-level synthesis did years ago, but ...

Why multiphysics analysis must move earlier in the design flow, and how a unified approach enables continuous validation from exploration through s ...

Schottky barriers at Si/metal interfaces; agentic HLS; probabilistic memory for edge; agentic HW design automation as repository-level code evolut ...

Cadence's Rajan Jani explains NVMe's Controller Memory Buffer feature, which exposes on-controller memory directly to the host system to reduce latency, improve PCIe fabric efficiency, and increase ...