GitHub

pyvauto - Python Verilog Auto-Generator

A Python Verilog automation tool that brings Emacs verilog-mode-style AUTO expansion to your editor. pyvauto is built for Vim (a Vim plugin is included): you get one-keystroke AUTOINST / AUTOARG / ...
IEEE

Generation of Synthesizable Verilog Code From Natural Language Specifications

Abstract: This study presents a method for generating synthesizable Verilog code for digital integrated circuits directly from natural-language specifications. The approach combines large language ...
GitHub

MCP server to run Python code in a sandbox.

We've decided to retire and archive this project - there's just no safe way to run Python within pyodide safely with reasonable latency. Instead, we're working hard on Monty which should solve the ...
IEEE

VToT: Automatic Verilog Generation via LLMs with Tree of Thoughts Prompting

Abstract: The automatic generation of Verilog code using Large Language Models (LLMs) presents a compelling solution to enhance the efficiency of hardware design flow. However, the state-of-the-art ...