IEEE

A 32Gb/s 0.36pJ/bit 3nm Chiplet IO Using 2.5D CoWoS Package with Real-Time and Per-Lane CDR ...

Abstract: This work presents a high density single-ended NRZ Chiplet IO in 3nm CMOS technology over 2.5D CoWoS interposer of up to 2mm trace length, with a total of 216 data lanes running ...